1. Technical Field of the Invention
The present invention relates an interleaver, useable in particular for the decoding of digital signals.
2. Description of Related Art
An interleaver is a unit for processing a digital data stream which changes the order of the data in the stream. Such an operation is useful, in particular, during transmission of a data stream: instead of irremediably affecting a small part of the data stream, any transmission errors are distributed over a large part of the stream, and are then able to be corrected using one of the correction methods known to the person skilled in the art. In general, transmission error correction combined with an interleaving operation is all the more effective as the order of the data in the stream may be regarded as random.
The data may be organized in the stream as successive data units, such as, for example, datagrams in the case of an IP transmission, cells in the case of an ATM transmission or frames in the case of a UMTS transmission.
To perform an interleaving of the data of the stream, the stream is chopped into stream slices of determined length. A stream slice generally comprises a large number of data units. The successive data of a slice are written to a random access memory according to a first determined ranking of the addresses of this memory, and are then read according to a second determined ranking of the addresses which differs from the first ranking. A change of order of the data in the stream, or interleaving, is thus obtained, which corresponds to the difference between the ranking of the addresses in respect of the writing of the data to the memory and the ranking of the addresses in respect of the reading of the data from the memory.
An interleaving of the data of the stream in the inverse order is obtained by exchanging the first and second rankings of the addresses between the memory read and write operations.
In a known manner, a working cycle of an interleaver comprises the following four phases, repeated for successive cycles:    1 writing of the successive data of a first stream slice to the memory, traversing the addresses of the memory according to a first ranking of said addresses;    2 reading of the data of the first stream slice from the memory, traversing the addresses of the memory according to a second ranking of said addresses;    3 writing of the successive data of a second stream slice to the memory, traversing the addresses of the memory according to the second ranking;    4 reading of the data of the second stream slice from the memory, traversing the addresses of the memory according to the first ranking.
Commonly, the first ranking of the addresses of the memory is the ascending numerical order of these addresses. The second ranking then corresponds to the order of interleaving. An interleaving operation consequently comprises a writing of the data according to the numerical order of the memory addresses, and a reading according to the interleaved order. Conversely, a deinterleaving operation comprises a writing of the data to the memory according to the interleaved order of the addresses, followed by a reading in the ascending numerical order of the addresses. During the working cycle of an interleaver described above, the first stream slice is interleaved, and the second stream slice is deinterleaved.
An advantage of this manner of working of the interleaver resides in the fact that the second and third phases of the cycle are performed simultaneously, as are the fourth and first phases of the cycle. A considerable interleaving/deinterleaving throughput is thus obtained. At each instant of a clock for regulating the interleaver, first data are therefore read from the memory and, simultaneously, second data are written to the memory. A dual port random access memory or DPRAM is commonly used for this purpose, so as to allow the two simultaneous operations of reading and writing. The capacity of the DPRAM memory is at least equal to the length of a stream slice.
A drawback of the use of a DPRAM memory resides in the considerable physical dimensions of the electronic component which constitutes this memory. This gives rise in particular to a high price of the memory component and bulkiness caused by this component within the interleaver.
There is accordingly a need to diminish the aforesaid drawbacks.